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データ保持性を利用したキャッシュのパワーゲーティング手法
https://ipsj.ixsq.nii.ac.jp/records/80000
https://ipsj.ixsq.nii.ac.jp/records/800000c5a0bd6-4a43-4b8e-9d43-5b7b0838e80a
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-ARC12198001.pdf (422.4 kB)
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Copyright (c) 2012 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | SIG Technical Reports(1) | |||||||
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| 公開日 | 2012-01-12 | |||||||
| タイトル | ||||||||
| タイトル | データ保持性を利用したキャッシュのパワーゲーティング手法 | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | 低消費電力技術 | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
| 資源タイプ | technical report | |||||||
| 著者所属 | ||||||||
| 東京大学 | ||||||||
| 著者所属 | ||||||||
| 東京大学 | ||||||||
| 著者所属 | ||||||||
| 東京大学 | ||||||||
| 著者所属 | ||||||||
| 東京大学 | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Tokyo University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Tokyo University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Tokyo University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Tokyo University | ||||||||
| 著者名 |
金均東
武田清大
三輪忍
中村宏
× 金均東 武田清大 三輪忍 中村宏
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | Caches consume large amount of leakage power because of their large area and massive transistors. To handle leakage power of caches, several works using power-gating(PG) was proposed . Even though PG is capable of high leakage saving, energy overhead by dismissing data is a big shortcoming of PG. In this paper, we focus on the data retentiveness of PG. This nature was not focused on previous works. Voltage of SRAM cell does not decrease to zero immediately after PG and this phenomenon is valuable to relive energy overhead for data recovery. We also propose a circuit to utilize data retentiveness. With the oracle knowledge control, we examined leakage saving potential of our proposal for L1 instruction and data cache. Results show that utilizing retentiveness of PG have big potential of leakage saving. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | Caches consume large amount of leakage power because of their large area and massive transistors. To handle leakage power of caches, several works using power-gating(PG) was proposed . Even though PG is capable of high leakage saving, energy overhead by dismissing data is a big shortcoming of PG. In this paper, we focus on the data retentiveness of PG. This nature was not focused on previous works. Voltage of SRAM cell does not decrease to zero immediately after PG and this phenomenon is valuable to relive energy overhead for data recovery. We also propose a circuit to utilize data retentiveness. With the oracle knowledge control, we examined leakage saving potential of our proposal for L1 instruction and data cache. Results show that utilizing retentiveness of PG have big potential of leakage saving. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AN10096105 | |||||||
| 書誌情報 |
研究報告計算機アーキテクチャ（ARC） 巻 2012-ARC-198, 号 1, p. 1-7, 発行日 2012-01-12 |
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| Notice | ||||||||
| SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
