| Item type |
SIG Technical Reports(1) |
| 公開日 |
2018-02-21 |
| タイトル |
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|
タイトル |
Pushing the Limits for 2D Convolution Computation On CUDA-enabled GPUs |
| タイトル |
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言語 |
en |
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タイトル |
Pushing the Limits for 2D Convolution Computation On CUDA-enabled GPUs |
| 言語 |
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言語 |
eng |
| キーワード |
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主題Scheme |
Other |
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主題 |
GPU |
| 資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_18gh |
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資源タイプ |
technical report |
| 著者所属 |
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Tokyo Institute of Technology／AIST-Tokyo Tech Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology |
| 著者所属 |
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National Institute of Advanced Industrial Science and Technology |
| 著者所属 |
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AIST-Tokyo Tech Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology |
| 著者所属 |
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Tokyo Institute of Technology／AIST-Tokyo Tech Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology |
| 著者所属(英) |
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en |
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Tokyo Institute of Technology / AIST-Tokyo Tech Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology |
| 著者所属(英) |
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|
en |
|
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National Institute of Advanced Industrial Science and Technology |
| 著者所属(英) |
|
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en |
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AIST-Tokyo Tech Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology |
| 著者所属(英) |
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|
en |
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Tokyo Institute of Technology / AIST-Tokyo Tech Real World Big-Data Computation Open Innovation Laboratory, National Institute of Advanced Industrial Science and Technology |
| 著者名 |
Peng, Chen
Mohamed, Wahib
Shinichiro, Takizawa
Satoshi, Matsuoka
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| 著者名(英) |
Peng, Chen
Mohamed, Wahib
Shinichiro, Takizawa
Satoshi, Matsuoka
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| 論文抄録 |
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内容記述タイプ |
Other |
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内容記述 |
The 2D convolution operator is the computational bottleneck in a variety of image processing and machine learning applications. We propose an algorithm to compute convolution by employing register files to cache image data (known as register cache), rather than using the user-managed scratch-pad memory. We take advantage of CUDA's warp shuffle functions to accelerate the intra-warp communication of partial results. Unlike the GEMM-based, FFT-based or Winograd method, our algorithm executes the convolution computation without using any GPU memory as a workspace, and is general to all filter shapes. Our algorithm performs better than state-of-the-art 2D convolution implementations. Using a single TitanXp GPU, it is in average 4.7x faster than NPP (Nvidia Performance Primitives), and 1.8x faster than the highly-optimized ArrayFire library. |
| 論文抄録(英) |
|
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内容記述タイプ |
Other |
|
内容記述 |
The 2D convolution operator is the computational bottleneck in a variety of image processing and machine learning applications. We propose an algorithm to compute convolution by employing register files to cache image data (known as register cache), rather than using the user-managed scratch-pad memory. We take advantage of CUDA's warp shuffle functions to accelerate the intra-warp communication of partial results. Unlike the GEMM-based, FFT-based or Winograd method, our algorithm executes the convolution computation without using any GPU memory as a workspace, and is general to all filter shapes. Our algorithm performs better than state-of-the-art 2D convolution implementations. Using a single TitanXp GPU, it is in average 4.7x faster than NPP (Nvidia Performance Primitives), and 1.8x faster than the highly-optimized ArrayFire library. |
| 書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AN10463942 |
| 書誌情報 |
研究報告ハイパフォーマンスコンピューティング（HPC）
巻 2018-HPC-163,
号 22,
p. 1-9,
発行日 2018-02-21
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| ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
2188-8841 |
| Notice |
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SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. |
| 出版者 |
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言語 |
ja |
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出版者 |
情報処理学会 |
IPSJ-HPC18163022.pdf (4.1 MB)
